Senior Mid-End ASIC Synthesis & Timing Lead (Hybrid)

Anysilicon; Austin (TX); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Positron AI in Austin, TX is seeking a Senior Mid-End ASIC Engineer to own synthesis, timing convergence, and RTL-to-netlist quality for our AI accelerator roadmap. This hands-on role requires transforming high-quality RTL into implementation-ready netlists while collaborating across architecture, RTL, and backend teams.

You will define synthesis methodology for current and future ASIC generations, drive timing closure, and optimize QoR using Cadence Genus or Design Compiler.

Qualifications

• 12+ years of ASIC implementation experience with successful tapeouts.
• Expertise in synthesis methodology and flow development.
• Deep knowledge of timing closure for complex designs.
• Proficiency in Cadence Genus and/or Synopsys Design Compiler.
• Strong SDC expertise and constraint development skills.
• Understanding of RTL design principles and implementation-friendly practices.
• Hands-on experience with advanced process nodes (5nm and below).
• Strong Tcl and Python scripting skills for automation.
• Excellent debugging and root-cause analysis capabilities.

Responsibilities

• Define and own synthesis methodology for current and future ASIC generations.
• Conduct hands-on synthesis using Cadence Genus and Synopsys Design Compiler.
• Develop and maintain SDC constraints and timing budgets.
• Drive logical timing closure and optimization across multiple parameters.
• Perform root-cause analysis of timing bottlenecks.
• Collaborate with architecture and RTL teams to mitigate timing risks.
• Partner with backend engineers for physical-aware optimization and timing budgeting.
• Lead cross-functional execution with various engineering teams to resolve issues rapidly.
• Serve as the synthesis technical lead with external partners, reviewing QoR and timing reports.
• Apply AI techniques to enhance timing analysis and engineering automation.

Skills

Synthesis methodolgy development

Timing closure optimization

Tcl and Python scripting

Debugging and root-cause analysis

Collaboration and cross-functional

Tools

Cadence Genus

Synopsys Design Compiler

Job description

Positron AI in Austin, TX is seeking a Senior Mid-End ASIC Engineer to own synthesis, timing convergence, and RTL-to-netlist quality for our AI accelerator roadmap. This hands-on role requires transforming high-quality RTL into implementation-ready netlists while collaborating across architecture, RTL, and backend teams.

You will define synthesis methodology for current and future ASIC generations, drive timing closure, and optimize QoR using Cadence Genus or Design Compiler.