Synthesis & Timing Closure Engineer for ASIC

LanceSoft, Inc.; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

LanceSoft, Inc. in San Jose, CA seeks an ASIC Synthesis + STA Engineer to drive full chip and block-level timing closure. You will develop timing constraints, perform synthesis and STA, and collaborate across Design, IP, Library, PNR, and RTL teams to ensure design quality and power intent alignment.

The role emphasizes cross-functional teamwork, methodology development, and the use of Synopsys tools, including PrimeTime and Design Compiler, for robust timing closure.

Qualifications

• 5+ years of experience in ASIC design required.
• Full chip and block-level timing closure experience preferred.
• Experience with Synopsys tools (PrimaPrimetime, Design Compiler, Formality) is required.

Responsibilities

• Develop full chip and block-level timing constraints.
• Perform synthesis and static timing analysis (STA) using Synopsys tools.
• Execute timing closure activities and support DMSA flows.
• Run and debug Formality and VCLP tools to validate design correctness.
• Collaborate with Design, IP, Library, PNR, and RTL teams to support implementation and power intent requirements.
• Contribute to methodology and flow development for synthesis, formal verification, STA, and timing closure.

Skills

Synthesis

STA

Timing closure

Constraints development

Cross-functional collaboration

Tools

Primetime

Design Compiler

Formality

VCLP

Job description

LanceSoft, Inc. in San Jose, CA seeks an ASIC Synthesis + STA Engineer to drive full chip and block-level timing closure. You will develop timing constraints, perform synthesis and STA, and collaborate across Design, IP, Library, PNR, and RTL teams to ensure design quality and power intent alignment.

The role emphasizes cross-functional teamwork, methodology development, and the use of Synopsys tools, including PrimeTime and Design Compiler, for robust timing closure.