Senior Front-End ASIC RTL Design & Sign-Off Lead

Synopsys, Inc.; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Synopsys, Inc. is seeking a Front-End ASIC Design Engineer with hands-on experience taking RTL from specification through design sign-off.

You will own RTL blocks for high-performance SoCs and drive synthesis and timing closure at the front-end boundary. You will ensure designs are clean against lint, CDC/RDC, timing, and power sign-off criteria before hand-off to physical design, contributing to methodology improvements and regression automation.

Qualifications

• 8+ years in ASIC design and STA sign-off.
• Front-end sign-off flows: STA, lint, CDC/RDC.
• SystemVerilog/Verilog RTL coding for synthesis.
• Synthesis and QoR analysis expertise.
• Low-power techniques: clock gating, power gating, multi-Vt, UPF.
• SDC constraint development and timing-closure methods.
• Scripting: TCL, Python, Perl; Linux/UNIX.
• AMBA AXI/AHB/APB knowledge and high-speed IP interfaces.

Responsibilities

• Drive front-end sign-off: STA, lint, CDC/RDC, synthesis, and power efficient design.
• Translate specifications into synthesizable RTL for blocks/subsystems.
• Own timing constraints development and support full-chip timing closure.
• Perform synthesis, QoR analysis, and RTL optimization for area, timing, congestion, and power.
• Apply formal property verification and assertion-based design to validate block behavior.
• Run power estimation and analysis and feed findings back into RTL optimization.
• Contribute to methodology, scripting, and regression automation.

Skills

SystemVerilog/Verilog RTL coding

Synthesis & QoR analysis

STA sign-off (PrimeTime)

Lint (SpyGlass)

CDC/RDC verification

Low-power design (UPF)

SDC timing constraints

Scripting (TCL, Python, Perl)

Linux/UNIX environment

AMBA AXI/AHB/APB protocols

High-speed IP integration (PCIe, DDR/Λ

Education

BS/MS in Electrical/Computer Engineering or related field

Tools

Design Compiler / Fusion Compiler

PrimeTime

SpyGlass

VC Formal / formal verification tools

Job description

Synopsys, Inc. is seeking a Front-End ASIC Design Engineer with hands-on experience taking RTL from specification through design sign-off.

You will own RTL blocks for high-performance SoCs and drive synthesis and timing closure at the front-end boundary. You will ensure designs are clean against lint, CDC/RDC, timing, and power sign-off criteria before hand-off to physical design, contributing to methodology improvements and regression automation.