Senior End-to-End ASIC Design Lead

Ralliant; Boulder (CO); Hybrid; USD 149,000 - 277,000; Full time

Job summary

Tektronix, a Tektronix division under Ralliant, seeks an ASIC Design Manager to lead digital ASIC design, verification, and physical design. You will guide architecture through tapeout, balancing performance, power, and area while interfacing with product and foundry teams.

You will mentor engineers, drive schedules, and ensure design quality across RTL, IP selection, and physical implementation in a fast-paced environment.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• Significant experience developing ASICs or complex digital ICs, including digital design and physical implementation.
• Experience leading technical projects and mentoring engineers across multidisciplinary teams.
• Strong knowledge of digital design methodologies: microarchitecture, SystemVerilog/Verilog RTL, IP integration, synthesis, constraints, and STA.
• Experience with physical design: floorplanning, clock-tree synthesis, place-and-route, timing closure, power integrity, and signoff.
• Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces.

Responsibilities

• Lead and mentor a team of digital ASIC design, verification, and physical design engineers.
• Own end-to-end digital ASIC development flow from architecture to tapeout.
• Set technical direction for digital IP, topology, and full-chip integration.
• Oversee physical design planning, floorplanning, power distribution, and timing closure.
• Coordinate with architecture, packaging, foundry, and external design-services teams.
• Drive design quality through reviews, lint/CDC checks, and signoff criteria.

Skills

Electrical engineering

ASIC design

Leadership

Verilog/SystemVerilog

Timing analysis

Cross-functional collaboration

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence tools

Synopsys

Job description

Tektronix, a Tektronix division under Ralliant, seeks an ASIC Design Manager to lead digital ASIC design, verification, and physical design. You will guide architecture through tapeout, balancing performance, power, and area while interfacing with product and foundry teams.

You will mentor engineers, drive schedules, and ensure design quality across RTL, IP selection, and physical implementation in a fast-paced environment.