Senior Synthesis & Timing Architect - AI ASIC (Remote)

Positron Corporation; United States; Remote; USD 200,000 - 300,000; Full time

Benefits offered by this job

Health insurance

Remote-first culture

401(k) with company match

Unlimited PTO

Visa support

Job summary

Positron AI in the United States is seeking a Senior Physical Design Engineer - Synth to own synthesis, timing convergence, and implementation readiness for key partitions across our AI accelerator roadmap.

This is a hands-on role turning high-quality RTL into implementation-ready netlists, developing timing constraints, and driving physical-aware optimization in collaboration with RTL designers and backend teams.

Qualifications

• 8+ years ASIC implementation experience with tapeouts
• Hands-on proficiency in synthesis and flow development
• Proven experience closing timing on complex designs
• Deep knowledge of Cadence Genus and/or Synopsys Design Compiler
• Strong SDC expertise and constraint development
• RTL design principles and implementation-friendly coding
• Experience with 7nm or below processes
• Tcl and Python scripting for automation and flow development
• Excellent debugging and root-cause analysis skills

Responsibilities

• Own synthesis for assigned partitions and deliver clean netlists
• Develop and improve synthesis flows and constraints
• Apply signoff criteria for synthesis deliverables
• Run hands-on synthesis with industry tools
• Develop and maintain SDC constraints and timing budgets
• Drive timing closure and identify bottlenecks
• Work with backend for physical-aware optimization
• Collaborate with architecture, RTL, verification, and IP teams
• Review QoR with external partners and improve methodologies

Skills

Synthesis

Timing closure

RTL-aware coding

Tcl/Python scripting

Root-cause analysis

Cross-functional collaboration

Tools

Cadence Genus

Synopsys Design Compiler

SDC constraints

MMMC environments

Job description

Positron AI in the United States is seeking a Senior Physical Design Engineer - Synth to own synthesis, timing convergence, and implementation readiness for key partitions across our AI accelerator roadmap.

This is a hands-on role turning high-quality RTL into implementation-ready netlists, developing timing constraints, and driving physical-aware optimization in collaboration with RTL designers and backend teams.