Senior ASIC Design Lead for AI Inference Chips

Positron Corporation; United States; À distance; USD 225 000 - 350 000; Plein temps

Résumé du poste

Positron AI is seeking a Senior ASIC Design Engineer to lead microarchitecture definition, RTL signoff, and PPA optimization for high-performance inference silicon. You will drive architectural tradeoffs, mentor junior engineers, and collaborate across architecture, verification, and physical design.

You will own SystemVerilog design, lead signoff checks, and coordinate with IP vendors and internal teams to deliver production-quality silicon on aggressive schedules.

Qualifications

• BS/MS in EE/CE (or related)
• Proven track record of leading designs from spec to signoff with strong PPA outcomes
• Deep SystemVerilog RTL expertise including clocking, resets, CDC/RDC handling, and protocol correctness
• Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites
• Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths
• Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications

Responsabilités

• Define and document microarchitecture for complex IP blocks/subsystems.
• Deliver production-quality, parameterized SystemVerilog RTL with interfaces, power/clock intent, and embedded assertions.

Connaissances

SystemVerilog RTL

Leadership

Cross-functional collaboration

EDA tools proficiency

AI/ML accelerator design

Formation

BS/MS in EE/CE

Outils

HBM/DDR

PCIe/CXL

AMBA AXI/ACE/CHI

cocotb/UVM

Description du poste

Positron AI is seeking a Senior ASIC Design Engineer to lead microarchitecture definition, RTL signoff, and PPA optimization for high-performance inference silicon. You will drive architectural tradeoffs, mentor junior engineers, and collaborate across architecture, verification, and physical design.

You will own SystemVerilog design, lead signoff checks, and coordinate with IP vendors and internal teams to deliver production-quality silicon on aggressive schedules.