Senior Front-End ASIC Design Engineer — RTL & Sign-off Lead

Synopsys Inc; Austin (TX); On-site; USD 120,000 - 210,000; Full time

Job summary

Synopsys Inc. in Austin, TX seeks a Front-End ASIC Design Engineer with hands-on RTL experience from specification through design sign-off.

You will own RTL blocks for high-performance SoCs, drive synthesis and timing closure quality at the front-end boundary, and ensure designs meet lint, CDC/RDC, timing and power sign-off criteria before hand-off to physical design. Responsibilities include translating specs to synthesizable RTL, managing SDCs, performing QoR analysis and RTL optimization, and

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.

Responsibilities

• Drive front-end sign-off: static timing analysis (STA), lint, CDC/RDC, synthesis, and power efficient design.
• Translate architectural specifications and micro-architecture documents into synthesizable RTL (SystemVerilog/Verilog) for blocks and subsystems.
• Own timing constraint (SDC) development and review; support full-chip timing closure.
• Perform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power.
• Apply formal property verification (VC Formal) and assertion-based design (SVA) to validate block behavior.
• Run power estimation and analysis (PrimePower) and feed findings back into RTL optimization.
• Contribute to methodology improvement, scripting, and regression automation.

Job description

Synopsys Inc. in Austin, TX seeks a Front-End ASIC Design Engineer with hands-on RTL experience from specification through design sign-off.

You will own RTL blocks for high-performance SoCs, drive synthesis and timing closure quality at the front-end boundary, and ensure designs meet lint, CDC/RDC, timing and power sign-off criteria before hand-off to physical design. Responsibilities include translating specs to synthesizable RTL, managing SDCs, performing QoR analysis and RTL optimization, and