Senior ASIC Design Lead - End-to-End Silicon

Tektronix, Inc.; Boulder (CO); On-site; USD 149,000 - 277,000; Full time

Job summary

Tektronix seeks an ASIC Design Manager to lead our digital ASIC design and realization team across Boulder/CO, Louisville/CO or Beaverton/OR. You will own the end-to-end digital ASIC flow, including microarchitecture, RTL development, IP selection, synthesis, floorplanning, timing closure, tapeout, and silicon bring-up.

You will mentor engineers, guide IP and subsystem design, manage schedules and risk, and collaborate with product architects and external partners to meet performance targets and

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Significant experience developing ASICs or complex digital ICs, including digital design and physical implementation activities.
• Experience leading technical projects, mentoring engineers, or coordinating work across multidisciplinary teams.
• Strong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis.
• Experience with physical design and implementation, including floorplanning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff.
• Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs.
• Experience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers.
• Experience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production release.

Responsibilities

• Lead digital ASIC design, verification, and physical design teams; establish priorities and mentor engineers.
• Own end-to-end digital ASIC development flow from architecture to tapeout, including IP selection and integration.
• Set technical direction for digital IP, subsystems, full-chip integration, and physical implementation.
• Drive physical design planning and execution including floorplanning, power-grid, clock distribution, and routing optimization.
• Coordinate with product and system architects to translate requirements into ASIC specs and performance targets.
• Oversee signoff activities: static timing analysis, signal integrity, power integrity, IR-drop, electromigration, DRC/LVS, and tapeout readiness reviews.
• Collaborate with packaging, foundry, and external design-services teams for die planning and package integration.
• Develop and execute project plans with program management, including schedules, resource plans, cost estimates, milestones, and risk mitigation.
• Recruit and retain engineering talent, manage contractors and external vendors as needed.
• Contribute to technical reviews and critical design work when needed to accelerate delivery.

Skills

Digital design

RTL design

SystemVerilog

Verilog RTL

IP integration

Synthesis

Constraints development

Static timing analysis

Timing closure

DFT

Leadership

Education

Bachelor's degree in Electrical Engineering or Computer Engineering or related technical discipline

Master’s or doctoral degree in Electrical/Computer Engineering or related field

Tools

Cadence

Synopsys

Siemens EDA

Job description

Tektronix seeks an ASIC Design Manager to lead our digital ASIC design and realization team across Boulder/CO, Louisville/CO or Beaverton/OR. You will own the end-to-end digital ASIC flow, including microarchitecture, RTL development, IP selection, synthesis, floorplanning, timing closure, tapeout, and silicon bring-up.

You will mentor engineers, guide IP and subsystem design, manage schedules and risk, and collaborate with product architects and external partners to meet performance targets and