Senior Memory Verification Architect (DDR6, SV/UVM)

Renesas Electronics Corp.; Duluth (MN); On-site; USD 130,000 - 170,000; Full time

Job summary

Renesas Electronics Corp. is seeking a Senior Staff Design Verification Engineer to provide technical leadership for verification of memory interface products used in data center, AI, and cloud applications. The role emphasizes DDR6 and future generations, with expert use of SystemVerilog and UVM.

The ideal candidate has 10+ years in semiconductor verification, can drive verification strategies, and mentor engineers.

Qualifications

• 10+ years in semiconductor verification.
• Experience driving verification strategies and mentoring engineers.

Responsibilities

• Provide technical leadership for verification of memory interface products.
• Focus on DDR6 and future generations using SystemVerilog and UVM.

Skills

SystemVerilog

UVM

Verification leadership

Mentoring engineers

Job description

Renesas Electronics is seeking a Senior Staff Design Verification Engineer to provide technical leadership for verification of memory interface products used in data center, AI, and cloud applications. The role focuses on DDR6 and future generations, with expert use of SystemVerilog and UVM.

The ideal candidate has 10+ years in semiconductor verification, can drive verification strategies, and mentor engineers.