Senior Memory Compiler Architect | Lead High-Performance IP

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Health benefits

Total rewards package

Job summary

Synopsys Inc invites a senior memory architect to design, develop, and evaluate physical IP—memory compilers (SRAM/RF/ROM/TCAM). You will optimize memory architecture, improve PPA, and collaborate cross-functionally to align with business goals.

You will mentor teammates, drive technical direction, and tackle complex engineering challenges in a dynamic environment within the memory IP team.

Qualifications

• 15+ years of experience in memory architecture and analog circuit design including schematic capture and functional verification.
• Significant experience in memory compiler flow.
• Proficiency in Python and Hspice/XA.
• Familiarity with industry standard verification tools for design and signoff flows.

Responsibilities

• Design, develop, and evaluate memory compiler IP (SRAM/RF/ROM/TCAM).
• Optimize memory architecture for best-in-class PPA and verification workflows.
• Collaborate with cross-functional teams to align deliverables with business goals.
• Contribute to technical direction and problem-solving within the engineering group.
• Mentor teammates and support technical growth.

Skills

Memory architecture

Embedded memory design

Python

Hspice/XA

Functional verification

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field

Tools

Industry standard verification tools

Job description

Synopsys Inc invites a senior memory architect to design, develop, and evaluate physical IP—memory compilers (SRAM/RF/ROM/TCAM). You will optimize memory architecture, improve PPA, and collaborate cross-functionally to align with business goals.

You will mentor teammates, drive technical direction, and tackle complex engineering challenges in a dynamic environment within the memory IP team.