Senior Memory Architect: High-Speed, Low-Power RAM Design

Lattice Semiconductor; San Jose (CA); On-site; USD 221,000 - 260,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

Lattice Semiconductor, with a major presence in San Jose, California, seeks a Sr. Memory Designer to lead the design of high-speed, low-power memory blocks for FPGA architectures.

You will own memory architecture, verification, and integration across the full design flow, collaborating with architecture and design teams to meet performance and yield targets. You will contribute to next-generation memory solutions, drive optimization, and ensure robust design practices while working in a

Qualifications

• Bachelor’s degree in electrical engineering; Master’s or PhD preferred.
• 10+ years in memory design, verification, validation, and integration.
• Strong knowledge of custom memory design and high-speed, low-power techniques.

Responsibilities

• Lead the design and development of custom memory circuits for SRAM and CRAM.
• Develop memory architectures and implement in advanced semiconductor technologies.
• Perform schematic capture, simulation, and margin verification of memory blocks.
• Oversee layout planning and ensure tight pitch-matched designs.
• Collaborate with architecture and design teams to define memory PPA and yield targets.
• Manage full embedded memory design flow from architecture to model generation.
• Bring innovative ideas to life in FPGA designs.

Skills

Memory design

High-speed design

Low-power design

FPGA memory configuration

Schematic capture & verification

Education

Bachelor's degree in electrical engineering

Master's or PhD preferred

Job description

Lattice Semiconductor, with a major presence in San Jose, California, seeks a Sr. Memory Designer to lead the design of high-speed, low-power memory blocks for FPGA architectures.

You will own memory architecture, verification, and integration across the full design flow, collaborating with architecture and design teams to meet performance and yield targets. You will contribute to next-generation memory solutions, drive optimization, and ensure robust design practices while working in a