Memory Compiler Design Engineer – SRAM/ROM

NXP Semiconductors; Austin (TX); Híbrido; USD 140.000 - 190.000; Jornada completa

Descripción de la vacante

NXP’s Austin Memories team is seeking an experienced memory circuit design engineer for SRAM and ROM internal memory compiler designs. The role focuses on CMOS memory circuit design to meet performance, power, and area targets, with support from periphery circuits for functional safety and scan functionality.

You will generate, execute, and evaluate simulations, work with layout on leaf cells, and collaborate with CAD/verification teams to ensure alignment with frontend models.

Formación

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline.
• 8+ years of industry experience in SRAM memory circuit design, including some design experience with advanced CMOS foundry technologies at 5nm and beyond.
• Strong familiarity with Cadence Virtuoso and other industry-standard EDA tools.
• Familiarity with automotive design rules and memory design requirements is a plus.
• Good knowledge of scripting languages such as Perl, tcl, or Python is a must.

Responsabilidades

• Design CMOS memory circuits to meet memory compiler performance, power, and area targets.
• Generate, execute, and evaluate simulation characterization measurements and test benches.
• Collaborate with layout teams on compiler leaf cell implementation to improve area and performance.
• Work with CAD teams to integrate designs into characterization, verification, and regression flows.
• Coordinate with modeling/verification to ensure consistency with frontend models and ATPG/emulation.

Conocimientos

CMOS memory design

Cadence Virtuoso

Automotive memory rules

Scripting in Perl

Scripting in Python

Scripting in Tcl

Analytical problem-solving

Educación

Bachelor's in Electrical/Computer Engineering

Master's degree preferred

Herramientas

Cadence Virtuoso

Descripción del empleo

NXP’s Austin Memories team is seeking an experienced memory circuit design engineer for SRAM and ROM internal memory compiler designs. The role focuses on CMOS memory circuit design to meet performance, power, and area targets, with support from periphery circuits for functional safety and scan functionality.

You will generate, execute, and evaluate simulations, work with layout on leaf cells, and collaborate with CAD/verification teams to ensure alignment with frontend models.