Principal Memory Architect: High-Performance SoC IP

MaxLinear; Carlsbad (CA); On-site; USD 135,000 - 198,000; Full time

Job summary

MaxLinear is seeking a senior memory IP engineer to design and optimize memory architectures for SoC integration. You will lead SRAM and register-file based solutions, leveraging memory compilers or custom designs to achieve high performance, low power, and area efficiency.

You will guide roadmaps, participate in architecture selection, and drive PPA trade-offs with multi-disciplinary teams and external IP vendors.

Qualifications

• Deep understanding of embedded SRAM and register-file architectures with bit-cell fundamentals and array layout considerations.
• Strong knowledge of low-power techniques, read/write assist, design robustness, margining, and power integrity considerations.
• Experience analyzing memory behavior across PVT corners and evaluating timing, reliability, signal integrity, and SoC-level trade-offs.
• Understanding of memory compiler flows and verification methodologies for both compiled and custom memories.
• Excellent communication and collaboration skills across multidisciplinary teams and strategic/hands-on influence.

Responsibilities

• Design, define, evaluate, and optimize memory IP across advanced technology nodes.
• Leverage memory architecture and system-level awareness to deliver high-performance, power-efficient memory solutions for SoC integration.
• Collaborate with IP and SoC teams to guide memory IP roadmaps, architecture selection, and trade-offs for PPA and robustness.
• Own design and optimization of memory architectures based on SRAMs, ROMs, and register files using memory compilers or custom designs.
• Deliver competitive memory IP solutions and enable seamless integration into SoCs.
• Work with cross-functional engineering teams and external IP vendors to develop scalable QA methodologies and verification frameworks.

Skills

Embedded SRAM

Register-file architectures

Low-power techniques

PVT timing and margins

Memory IP verification

Cross-functional collaboration

Communication skills

Education

BS in Electrical Engineering (or higher)

Tools

HSPICE

Spectre

Python

Cadence Virtuoso

Job description

MaxLinear is seeking a senior memory IP engineer to design and optimize memory architectures for SoC integration. You will lead SRAM and register-file based solutions, leveraging memory compilers or custom designs to achieve high performance, low power, and area efficiency.

You will guide roadmaps, participate in architecture selection, and drive PPA trade-offs with multi-disciplinary teams and external IP vendors.