Senior Memory Architect for HPC ASICs & Edge AI

MediaTek Research Lab Inc.; San Jose (CA); Hybrid; USD 221,000 - 301,000; Full time

Benefits offered by this job

Health insurance

Life insurance

Disability insurance

401K

Paid time off

Parental leave

Company paid holidays

Savings plan

Job summary

MediaTek Research Lab Inc. in San Jose, CA is seeking a Principal Memory Design Engineer/Senior Technical Manager with 10+ years in embedded memories to architect high‑performance memory circuits for HPC ASICs and Data Center AI workloads.

You will lead DTCO initiatives, collaborate with Data Center customers and cross‑functional teams to deliver SRAM, TCAM, CIM and related memories, and mentor designers while staying hands‑on.

Qualifications

• PhD or master's degree in electrical engineering or related field.
• 10+ years of hands-on experience designing embedded memories (SRAM, TCAM) for high-performance processors or ASICs in advanced technology nodes.
• Experience with DTCO and pathfinding for semi-custom and custom designs is desirable.
• Deep expertise in digital circuit design techniques, particularly in FinFET and Gate-All‑Around technologies.
• Experience with the full design cycle of SRAM and memory compiler development.
• Familiarity with Logic Equivalence Checking (LEC) tools such as ESPCV.
• Capable of reviewing and coordinating layout activities & IR-EM signoff.
• Familiarity with transistor level STA tools such as NanoTime.
• Demonstrated experience in silicon debugging and bring-up.
• Experience with semi-custom design flows, including RTL synthesis, DV, APR, and STA, is desirable.
• Proficient in scripting languages such as Perl and Python.
• Strong analytical & problem-solving skills with excellent communication & leadership abilities.

Responsibilities

• Work with Data Center AI ASIC customers to co-develop embedded memory architectures and circuits.
• Define, design, and deliver high-performance, customized memory solutions including SRAM, TCAM, CIM, and NMC macros.
• Lead Design Technology Co-Optimization (DTCO) and pathfinding initiatives for semi-custom and custom SRAM designs.
• Lead end-to-end design of dual-rail custom memories meeting PPA specs.
• Drive innovation by integrating specialized circuits to achieve industry-leading PPA.
• Provide mentorship and technical direction while remaining hands-on in memory architectures.
• Evaluate and implement new design methodologies and tools to enhance productivity and quality.
• Collaborate with global design and CAD teams to manage multiple tasks.

Skills

Digital circuit design

Leadership

Problem-solving

Analytical thinking

Cross-functional collaboration

Communication

Education

PhD in Electrical Engineering

Master's in Electrical Engineering

Tools

ESPCV

NanoTime

RTL synthesis

DV/STA flows

Job description

MediaTek Research Lab Inc. in San Jose, CA is seeking a Principal Memory Design Engineer/Senior Technical Manager with 10+ years in embedded memories to architect high‑performance memory circuits for HPC ASICs and Data Center AI workloads.

You will lead DTCO initiatives, collaborate with Data Center customers and cross‑functional teams to deliver SRAM, TCAM, CIM and related memories, and mentor designers while staying hands‑on.