Memory Compiler Engineer - SRAM & IP Design

Apple Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 176,000 - 312,000; Full time

Job summary

Apple Inc. in Santa Clara, California, is seeking a Compiler Circuit Design Engineer to lead SRAM/Reg file IP development for high-performance, low-power designs.

You will collaborate with compiler vendors and design teams to drive IP requirements, design validation, and end-to-end integration, leveraging strong device physics knowledge and leadership experience. This role emphasizes delivering PPA goals and mass production readiness.

Qualifications

• BS and a minimum of 10 years of relevant industry experience.
• 5+ years circuit design experience.
• Expertise in high-performance low-power circuit design and SRAM/register file arrays.
• Knowledge of circuit simulation and design tools.
• Experience leading multi-functional teams and presenting to multi-level audiences.
• Understanding of device physics and process.
• Experience driving failure analysis and yield improvements.
• Exposure to ML-based programming algorithms.
• Ability to automate design processes.

Responsibilities

• Drive the development of SRAM, register files and latch arrays to enable high performance and low power design.
• Understand SRAM compiler IP requirements and coordinate with Vendors and internal IP teams.
• Lead SRAM compiler IP requirements to Vendors and internal IP teams.
• Understand the complete spectrum of design flow, DFT and testing aspects of the compiler IPs.
• Work with logic/architecture teams to capture specifications of SRAM/Reg files/Latch arrays and drive the implementation.

Skills

SRAM design

Register files

Low power design

DFT/testing

Leadership

Automation

Device physics

ML algorithms

Education

Bachelor's degree in Electrical Engineering or related

Tools

Circuit simulation tools

Top-level integration tools

EDA tools

Job description

Apple Inc. in Santa Clara, California, is seeking a Compiler Circuit Design Engineer to lead SRAM/Reg file IP development for high-performance, low-power designs.

You will collaborate with compiler vendors and design teams to drive IP requirements, design validation, and end-to-end integration, leveraging strong device physics knowledge and leadership experience. This role emphasizes delivering PPA goals and mass production readiness.