Senior IC Package Layout Lead (2.5D/3D-IC)

Amazon Web Services (AWS); Portland (OR); On-site; USD 185,000 - 288,000; Full time

Benefits offered by this job

Health insurance

RSUs

Paid time off

Job summary

Annapurna Labs (U.S.) Inc. in the USA is seeking a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for next-generation ML and data center ASICs.

You will own the package layout from floor planning through tape-out, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. You will drive cross-level optimization across die RDL, interposer/substrate, and PCB to ensure optimal power delivery and high-speed

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• 10+ years of IC package layout and physical design experience.
• Proven track record leading package designs from concept through tape-out for complex substrates or interposers.
• Hands-on experience with package layout tools (Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition).
• Deep understanding of advanced packaging technologies: 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbump, silicon bridge interconnects.

Responsibilities

• Lead full package layout cycle from floor planning to tape-out release.
• Drive physical design of advanced packaging architectures (2.5D/3D-IC, fan-out WLP).
• Define and optimize package floorplans with power/ground, impedance and routing considerations.
• Collaborate with OSAT partners and foundries for DFM and manufacturability.

Skills

IC packaging

Physical design

RDL routing

Power/ground plane design

Education

Bachelor's degree in Electrical Engineering

Master's degree or equivalent

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs (U.S.) Inc. in the USA is seeking a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for next-generation ML and data center ASICs.

You will own the package layout from floor planning through tape-out, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. You will drive cross-level optimization across die RDL, interposer/substrate, and PCB to ensure optimal power delivery and high-speed