Senior Debug Verification Engineer (UVM/SoC)

Altera Corporation; San Jose, Northern (CA, KY); Hybrid; USD 149,000 - 215,000; Full time

Job summary

Altera Corporation in San Jose, California, is seeking a Sr. Debug Design Verification Engineer to lead pre-silicon verification for SoC, FPGA and full-chip designs, and to develop test cases and UVM testbenches.

The role requires defining verification strategies and coordinating with Design, SW and Architecture teams to achieve full coverage. Responsibilities include pre-silicon verification, testbench creation, and debugging architecture (JTAG, USB, PCIe).

Qualifications

• 8+ years of experience with complex ASIC designs and/or verification.
• 8+ years of SystemVerilog language experience.
• 8+ years of experience on UVM verification methodology, and formal verification method.
• 8+ years of scripting in Linux/Unix environments, with Perl and/or Python desirable.
• Strong communication skills and ability to work with a team spread across different geography sites.

Responsibilities

• Pre-silicon system verification for SoC, FPGA, and full-chip designs.
• Create test cases and testbenches using UVM.
• Define verification strategies, methodology and test plans for full coverage.
• Coordinate cross-functional efforts with Design, SW, and Architecture teams to achieve full coverage.
• Experience with Design for Debug (JTAG, High-speed USB, PCIe) architectures; Emulation experience is a plus.

Skills

SystemVerilog

UVM

ASIC verification

Testbench development

Emulation

Tools

Linux/Unix scripting

Perl

Python

Emulation tools

Debug architectures

Job description

Altera Corporation in San Jose, California, is seeking a Sr. Debug Design Verification Engineer to lead pre-silicon verification for SoC, FPGA and full-chip designs, and to develop test cases and UVM testbenches.

The role requires defining verification strategies and coordinating with Design, SW and Architecture teams to achieve full coverage. Responsibilities include pre-silicon verification, testbench creation, and debugging architecture (JTAG, USB, PCIe).