Senior IP Verification Architect - PCIe/CXL, Hybrid

AMD; San Jose (CA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

AMD is seeking a Lead IP Verification Engineer in San Jose, CA to drive front-end verification for PCIe and CXL IP. You will architect UVM environments, collaborate with cross-functional teams, and deliver first-pass silicon success for next-gen IP solutions.

Ideal candidates have deep expertise in SystemVerilog, Verilog, and high-speed protocol verification, with strong leadership and communication skills across distributed teams.

Qualifications

• ASIC/IP verification experience using UVM methodology.
• Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
• Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
• Proficiency in scripting and automation using Python, Perl, or similar languages.
• Experience working across the ASIC/FPGA development lifecycle from planning through tape‑out.

Responsibilities

• Architect and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components.
• Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
• Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
• Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
• Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency and productivity.

Skills

UVM verification

SystemVerilog

Verilog

PCIe/CXL protocols

Python/Perl scripting

ASIC/FPGA lifecycle

Technical leadership

Team collaboration

Communication

Education

Electrical/CS degree

Job description

AMD is seeking a Lead IP Verification Engineer in San Jose, CA to drive front-end verification for PCIe and CXL IP. You will architect UVM environments, collaborate with cross-functional teams, and deliver first-pass silicon success for next-gen IP solutions.

Ideal candidates have deep expertise in SystemVerilog, Verilog, and high-speed protocol verification, with strong leadership and communication skills across distributed teams.