Design Verification Lead — PCIe/CXL & High‑Speed IP

Advanced Micro Devices

San Jose (CA)

On-site

USD 140,000 - 210,000

Full time

14 days+
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Job summary

Advanced Micro Devices (AMD) seeks a Design Verification Engineer Lead in the AECG Group based in San Jose, CA. You will lead front-end design and integration efforts for FPGA/ASIC IP verification and first-pass silicon success for PCIe and CXL-based solutions.

You will collaborate across architecture, IP design, physical design, firmware and product engineering, shaping verification strategies, developing UVM environments, and mentoring distributed teams.

Qualifications

  • Minimum 10 years of design verification experience using UVM.
  • Strong expertise in SystemVerilog, Verilog, and object‑oriented programming.
  • Experience verifying high‑speed protocols (PCIe, CXL, 400G Ethernet) is preferred.

Responsibilities

  • Collaborate with architects, hardware designers, and firmware teams to verify PCIe, CXL, and high‑speed connectivity features.
  • Develop verification plans addressing feature interactions, HW/SW integration, performance, and system‑level use cases.
  • Design and implement IP or subsystem‑level UVM verification environments (monitors, scoreboards, checkers, reusable verification components).
  • Develop directed and constrained‑random tests, run regressions, debug failures to achieve high functional coverage.
  • Drive verification automation and AI‑assisted tools adoption to improve efficiency.

Skills

SystemVerilog
Verilog
UVM
OOP
Python
Perl
Digital design

Education

Bachelor's / Master's in EE/CS

Tools

UVM environment tools

Job description

Advanced Micro Devices (AMD) seeks a Design Verification Engineer Lead in the AECG Group based in San Jose, CA. You will lead front-end design and integration efforts for FPGA/ASIC IP verification and first-pass silicon success for PCIe and CXL-based solutions.

You will collaborate across architecture, IP design, physical design, firmware and product engineering, shaping verification strategies, developing UVM environments, and mentoring distributed teams.

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