Design Verification Lead – PCIe/CXL IP, AI-Driven QA

AMD; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD in San Jose, CA is seeking a Design Verification Engineer Lead to advance FPGA/ASIC IP verification. You will work across architecture, IP design, physical design and firmware teams to ensure first-pass silicon success for high-speed IP solutions.

You bring deep UVM-based verification expertise, SystemVerilog and Python scripting, plus leadership experience mentoring distributed teams. This role emphasizes collaboration and technical excellence.

Qualifications

• Minimum 10 years of design verification experience using UVM methodology.
• Strong expertise in SystemVerilog, Verilog, and object-oriented programming.
• Experience verifying PCIe, CXL, and high-speed protocols; ASIC/FPGA lifecycle exposure.

Responsibilities

• Collaborate with architects, hardware designers, and firmware teams to verify PCIe, CXL, and high-speed features.
• Develop verification plans covering interactions, integration, performance and system use cases.
• Design and implement UVM environments with monitors, scoreboards and checkers.
• Develop directed and constrained-random tests; run regressions and debug failures.
• Drive verification automation and AI-assisted tooling adoption for efficiency.

Skills

UVM-based verification

SystemVerilog

Python scripting

Verilog

Leadership/mentoring

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in related field

Tools

Questa

VCS

Job description

AMD in San Jose, CA is seeking a Design Verification Engineer Lead to advance FPGA/ASIC IP verification. You will work across architecture, IP design, physical design and firmware teams to ensure first-pass silicon success for high-speed IP solutions.

You bring deep UVM-based verification expertise, SystemVerilog and Python scripting, plus leadership experience mentoring distributed teams. This role emphasizes collaboration and technical excellence.