Lead IP Verification Architect: PCIe/CXL & AI Tools

Advanced Micro Devices, Inc.; San Jose (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose, CA seeks a Lead IP Verification Engineer in the AECG Group to drive front-end verification for FPGA and ASIC IP.

You will design and implement UVM-based environments and collaborate with architecture, IP design, physical design, firmware, and product teams to ensure first-pass silicon success for PCIe and CXL solutions. The ideal candidate has deep SystemVerilog/Verilog expertise, strong leadership, and a track record mentoring distributed teams.

Qualifications

• ASIC/IP verification experience using UVM methodology.
• Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
• Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
• Proficiency in scripting and automation using Python, Perl, or similar languages.
• Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
• Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements.
• Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.

Responsibilities

• Architect and implement IP or subsystem-level UVM verification environments (monitors, scoreboards, checkers).
• Collaborate with architects, hardware designers, and firmware teams to verify PCIe, CXL, and high-speed features.
• Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
• Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
• Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency.

Skills

ASIC/IP verification

UVM

SystemVerilog

Verilog

Object-oriented programming

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science

Job description

Advanced Micro Devices, Inc. in San Jose, CA seeks a Lead IP Verification Engineer in the AECG Group to drive front-end verification for FPGA and ASIC IP.

You will design and implement UVM-based environments and collaborate with architecture, IP design, physical design, firmware, and product teams to ensure first-pass silicon success for PCIe and CXL solutions. The ideal candidate has deep SystemVerilog/Verilog expertise, strong leadership, and a track record mentoring distributed teams.