Senior PCIe Verification Architect (Gen4/5) - UVM, Equity

SiMa.ai; San Jose (CA); On-site; USD 220,000 - 296,400; Full time

Benefits offered by this job

Equity

Job summary

SiMa.ai in San Jose, CA is seeking a Principal Engineer for PCIe Verification to lead formal verification efforts for PCIe controllers and PHYs across block, sub‑system, and MLSoC levels.

You will drive PCIe bring‑up, debug on emulation, and work on UCIe interface verification on next‑gen projects, collaborating with architectures and MLSoC teams. The role requires deep SV/UVM experience and strong programming skills.

Qualifications

• BS/MS in Electrical Engineering or Computer Science with 12+ years of experience in functional verification and silicon bring‑up/debug.
• Strong experience with UVM and SystemVerilog based verification methodologies.
• Experience with PCIe Gen4/5 and PCIe bring‑up on silicon is a plus.
• Proficiency in C/C++/Python programming is a plus.

Responsibilities

• Participate in PCIe architecture discussions and reviews.
• Define and develop PCIe test bench components using UVM & SystemVerilog.
• Bring up and test PCIe in block and full‑chip environments.
• Develop and execute a test plan for PCIe verification.
• Verify PCIe EP/RC functionality and measure performance.
• Lead code coverage reviews and closure; SystemVerilog assertion coverage.

Skills

UVM

SystemVerilog

C/C++/Python

Education

Bachelor/Master in Electrical Engineering or Computer Science

Job description

SiMa.ai in San Jose, CA is seeking a Principal Engineer for PCIe Verification to lead formal verification efforts for PCIe controllers and PHYs across block, sub‑system, and MLSoC levels.

You will drive PCIe bring‑up, debug on emulation, and work on UCIe interface verification on next‑gen projects, collaborating with architectures and MLSoC teams. The role requires deep SV/UVM experience and strong programming skills.