Senior Interface IP Verification Architect

Synopsys Inc; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Health benefits

Wellness programs

Professional development

Job summary

Synopsys Inc in Austin is seeking an experienced ASIC Verification Engineer who will own verification of complex Interface IP such as PCIe, CXL, DDR, and Ethernet. You will develop scalable UVM-based verification environments and work with architects, RTL, firmware, and systems teams to ensure high-quality silicon.

You'll define verification strategies, write constrained-random tests, drive coverage closure, and mentor peers across distributed teams.

Qualifications

• BSEE required with 8–10+ years in ASIC/SoC verification.
• Deep SystemVerilog and UVM expertise.
• Strong knowledge of PCIe, CXL, DDR, Ethernet.
• Experience with VCS or ModelSim.

Responsibilities

• Own verification of PCIe, CXL, DDR, Ethernet interfaces.
• Develop scalable UVM-based verification environments.
• Define test plans and drive coverage closure.
• Collaborate with architects, RTL, firmware, and systems teams.

Skills

SystemVerilog

UVM

PCIe

CXL

DDR

Ethernet

Education

BSEE

Tools

VCS

ModelSim

Job description

Synopsys Inc in Austin is seeking an experienced ASIC Verification Engineer who will own verification of complex Interface IP such as PCIe, CXL, DDR, and Ethernet. You will develop scalable UVM-based verification environments and work with architects, RTL, firmware, and systems teams to ensure high-quality silicon.

You'll define verification strategies, write constrained-random tests, drive coverage closure, and mentor peers across distributed teams.