Lead IP Verification Engineer

Advanced Micro Devices, Inc.; San Jose (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose, CA seeks a Lead IP Verification Engineer in the AECG Group to drive front-end verification for FPGA and ASIC IP.

You will design and implement UVM-based environments and collaborate with architecture, IP design, physical design, firmware, and product teams to ensure first-pass silicon success for PCIe and CXL solutions. The ideal candidate has deep SystemVerilog/Verilog expertise, strong leadership, and a track record mentoring distributed teams.

Qualifications

• ASIC/IP verification experience using UVM methodology.
• Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
• Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
• Proficiency in scripting and automation using Python, Perl, or similar languages.
• Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
• Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements.
• Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.

Responsibilities

• Architect and implement IP or subsystem-level UVM verification environments (monitors, scoreboards, checkers).
• Collaborate with architects, hardware designers, and firmware teams to verify PCIe, CXL, and high-speed features.
• Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
• Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
• Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency.

Skills

ASIC/IP verification

UVM

SystemVerilog

Verilog

Object-oriented programming

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shapingthefuture.

Whetheryou'redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger- technologythat moves the world forward.Join us and, together, we'll advance your career.

THE ROLE

As a Lead IP Verification Engineer in the AECG Group, you will help bring to life cutting-edge FPGA and ASIC solutions for a broad range of customers. As a member of the front-end design verification team, you will collaborate closely with architecture, IP design, physical design, firmware, and product engineering teams to deliver first-pass silicon success for next-generation PCIe and CXL-based IP solutions.

THE PERSON

You are passionate about complex IP architectures, digital design, and advanced verification methodologies. You thrive in a collaborative environment, enjoy solving challenging technical problems, and have a proven ability to work effectively across global teams. You bring strong analytical skills, technical leadership, and a continuous learning mindset.

The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES

• Architect and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components.

• Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
• Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
• Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
• Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency and productivity.

REFERRED EXPERIENCE

• ASIC/IP verification experience using UVM methodology.
• Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
• Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
• Proficiency in scripting and automation using Python, Perl, or similar languages.
• Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
• Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements.
• Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.
• Knowledge of computer architecture, system-level design concepts, and emerging AI-driven verification methodologies is a plus.

ACADEMIC CREDENTIALS

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

LOCATION

San Jose, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.