Lead Design Verification Architect – CXL/PCIe/Ethernet

Astera Labs; San Jose (CA); Hybrid; USD 185,000 - 230,000; Full time

Job summary

Astera Labs in San Jose is seeking a Principal/Senior Principal Design Verification Engineer to lead the verification of next‑gen connectivity IPs and SoCs powering AI and cloud infrastructure.

You will define verification strategies, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon to ensure first‑pass silicon success.

The ideal candidate has deep protocol verification expertise and enjoys solving complex architectural challenges.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.
• Strong expertise in SystemVerilog and UVM.
• Extensive experience in verification planning, execution, and sign-off.
• Deep understanding of constrained-random verification and coverage-driven methodologies.
• Strong experience with assertions (SVA), functional coverage, and protocol compliance.
• Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.

Responsibilities

• Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.
• Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.
• Drive verification planning, execution, coverage closure, and sign-off.
• Identify verification risks early and proactively drive mitigation plans.
• Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.
• Architect and develop scalable UVM/System Verilog verification environments.
• Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.
• Debug complex RTL, protocol, timing, and integration issues.
• Drive regression planning, automation, and continuous integration improvements.
• Develop reusable VIP and verification infrastructure across multiple product lines.

Skills

SystemVerilog

UVM

Constrained-random verification

Coverage-driven verification

Debug RTL/protocols

SVA assertions

Simulation debugging

Education

Bachelor's or Master's in Electrical Engineering or related field

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

Astera Labs in San Jose is seeking a Principal/Senior Principal Design Verification Engineer to lead the verification of next‑gen connectivity IPs and SoCs powering AI and cloud infrastructure.

You will define verification strategies, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon to ensure first‑pass silicon success.

The ideal candidate has deep protocol verification expertise and enjoys solving complex architectural challenges.