Senior IO/Clocking Design Engineer – DRAM (High-Speed)

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 150,000 - 210,000; Full time

Job summary

Micron Technology is seeking a Principal IO/Clocking Design Engineer to join our design team working on high-speed IO and clocking circuits for DRAM products. You will develop, optimize, verify, and fan out circuits across memory projects.

You will model performance, analyze clock jitter and data-path impairment, mentor engineers, and collaborate with process integration and silicon validation teams on next-generation nodes.

Qualifications

• MSEE with 10+ years or BSEE with 12+ years in analog/mixed-signal circuit design.
• Proficiency with UNIX and Cadence design tools.
• Understanding of device physics and CMOS processing techniques.
• Ability to supervise layout and understand good layout practices for high-speed circuits to minimize parasitic impacts.
• Strong communication skills to convey technical concepts verbally and in writing.
• Able to work across multiple product types and silicon validation efforts.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply proven high-speed circuit design techniques and enhance evaluation of IO data path and clocking path at circuit level.
• Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics.
• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities.
• Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node.

Skills

High-speed IO/Clocking Design

Transmitter/Receiver/Clocking

CMOS Analog/Mixed-Signal

Scripting: Python/Perl

UNIX

Education

MSEE

BSEE

Tools

Cadence

UNIX

Job description

Micron Technology is seeking a Principal IO/Clocking Design Engineer to join our design team working on high-speed IO and clocking circuits for DRAM products. You will develop, optimize, verify, and fan out circuits across memory projects.

You will model performance, analyze clock jitter and data-path impairment, mentor engineers, and collaborate with process integration and silicon validation teams on next-generation nodes.