Senior IO/Clocking Design Engineer — High-Speed DRAM IP

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time off and holidays

Paid family leave

Job summary

1000 Micron Technology, Inc. is looking for an experienced IO/Clocking Design Engineer at SMTS level to develop critical high-speed IP circuits for DRAM products. This role involves architecture, design, optimization, and technical support, focusing on circuit performance and IO impairments.

Candidates should have strong design experience and be able to mentor early-career engineers. Micron also offers competitive benefits, including health plans and paid time off. Relocation to Boise, Idaho is required for this position.

Qualifications

• Minimum MSEE + 10 years or BSEE + 12 years of relevant experience.
• Ability to supervise high-speed circuit layout work.
• Strong communication skills for conveying technical concepts.

Responsibilities

• Define, innovate, design, optimize and verify high‑speed IO and clocking circuits for DRAM products.
• Develop modeling and simulation methodologies to capture circuit performance metrics.
• Collaborate with process integration and transistor modeling teams.

Skills

High-speed IO interface design

Timing and clocking circuits

Communication skills

Mentoring early-career engineers

Education

MSEE or BSEE with experience

Job description

1000 Micron Technology, Inc. is looking for an experienced IO/Clocking Design Engineer at SMTS level to develop critical high-speed IP circuits for DRAM products. This role involves architecture, design, optimization, and technical support, focusing on circuit performance and IO impairments.

Candidates should have strong design experience and be able to mentor early-career engineers. Micron also offers competitive benefits, including health plans and paid time off. Relocation to Boise, Idaho is required for this position.