Senior DRAM IO & Clock Design Architect

Micron Technology; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Relocation assistance

Comprehensive benefits (medical,Dental

Vision, PTO & holidays

Job summary

Micron Technology, a world leader in memory and storage, seeks a Principal/ MTS IO/Clock Design Engineer to lead high-speed IO and clocking circuit design for DRAM IP. You will drive modeling, verification and optimization, addressing jitter, timing and performance at full-chip level.

Relocation to Micron’s Boise headquarters is required. The role collaborates with design, SI, and process teams, mentoring engineers and advancing next-generation process nodes.

Qualifications

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with strong background in designing high-speed IO interface, timing and clocking circuits with proven silicon successes.
• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts.
• Strong interpersonal skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written.
• Mental agility and ability to multi-task across multiple product families and silicon validation efforts.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply robust high-speed circuit design techniques and enhance timing/jitter sensitivity of IO and clock paths at circuit and full-chip level.
• Develop modeling, analysis and simulation methodology to capture key circuit performance metrics and impacts to specifications.
• Collaborate with Product Engineering, SI teams and process/EDA partners to optimize silicon and AI-assisted design flows.

Skills

High-speed IO design

Clocking circuits

Timing and jitter analysis

Mentoring engineers

Education

MSEE

BSEE with experience

Tools

Cadence

Synopsys

Mentor Graphics

Job description

Micron Technology, a world leader in memory and storage, seeks a Principal/ MTS IO/Clock Design Engineer to lead high-speed IO and clocking circuit design for DRAM IP. You will drive modeling, verification and optimization, addressing jitter, timing and performance at full-chip level.

Relocation to Micron’s Boise headquarters is required. The role collaborates with design, SI, and process teams, mentoring engineers and advancing next-generation process nodes.