Senior IO & Clocking Design Engineer – DRAM High-Speed

Micron Technology, Inc.; Boise (ID); Hybrid; USD 150,000 - 200,000; Full time

Job summary

Micron Technology, Inc. in Boise, Idaho, seeks a Principal IO/Clocking Design Engineer to develop and verify high-speed IO circuits for DRAM products. You will optimize timing, model and simulate, and push performance across configurations.

You will collaborate with Product Engineering and SI teams, mentor junior engineers, and contribute to next-gen process nodes while ensuring robust circuit performance in a fast-paced environment.

Qualifications

• MSEE with 10+ years or BSEE with 12+ years of industry experience in analog and mixed-signal circuit design.
• Proficiency with UNIX and Cadence design environment (simulation, schematic entry, SPF extraction).
• Understanding of device physics and basic CMOS processing techniques.
• Ability to supervise layout work and apply good layout practices for high-speed circuits.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits for DRAM products.
• Apply high-speed circuit design techniques and enhance performance evaluation at circuit, full-chip and system levels.
• Collaborate with Product/Si teams to compare silicon performance with simulations and support correlation.

Skills

High-speed IO design

Transmitter/Receiver/Clocking

Analog & Mixed-Signal design

Device physics / CMOS

Scripting: Python/Perl

Mentoring/leadership

AI/ML tooling

Education

MSEE + 10+ years

BSEE + 12+ years

Tools

Cadence

UNIX

Job description

Micron Technology, Inc. in Boise, Idaho, seeks a Principal IO/Clocking Design Engineer to develop and verify high-speed IO circuits for DRAM products. You will optimize timing, model and simulate, and push performance across configurations.

You will collaborate with Product Engineering and SI teams, mentor junior engineers, and contribute to next-gen process nodes while ensuring robust circuit performance in a fast-paced environment.