Principal DRAM IO/Clocking Architect

Micron; Boise (ID); On-site; USD 140,000 - 190,000; Full time

Job summary

Micron Technology seeks a Senior/Principal SMTS in High-speed IO/Clocking Design Engineering to join our Boise, Idaho team. Relocation to Micron's Boise campus is required, with a focus on defining, designing and verifying IO and clocking circuits for next-generation DRAM products.

You will collaborate with Product Engineering, SI and process integration teams, mentor engineers, and drive robust design practices, timing and jitter analysis, and full-chip verification across product types.

Qualifications

• MSEE with 10+ years or BSEE with 12+ years in high-speed IO/timing circuit design.
• Ability to supervise layout and minimize parasitics in high-speed circuits.
• Strong communication and mentoring skills for cross-functional teams.

Responsibilities

• Define, design, implement, optimize and verify high-speed IO and clocking circuits for new DRAM products.
• Apply robust high-speed circuit design techniques and evaluate timing and jitter of IO/data paths at circuit and full-chip level.
• Develop accurate modeling, analysis and simulation methods for key metrics and their impact to specs.
• Collaborate with Product Engineering and SI teams to compare silicon performance with simulations.
• Work with process integration and transistor modeling teams on next-generation process nodes.

Skills

High-speed IO design

Timing & clocking

Mentoring engineers

Communication

Silicon validation

Education

MSEE

BSEE

Tools

PERL

Python

Channel modeling

Job description

Micron Technology seeks a Senior/Principal SMTS in High-speed IO/Clocking Design Engineering to join our Boise, Idaho team. Relocation to Micron's Boise campus is required, with a focus on defining, designing and verifying IO and clocking circuits for next-generation DRAM products.

You will collaborate with Product Engineering, SI and process integration teams, mentor engineers, and drive robust design practices, timing and jitter analysis, and full-chip verification across product types.