Senior IO/Clocking Design Engineer, DRAM

Micron; Boise (ID); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Paid holidays

Job summary

Micron Technology in Boise, Idaho, invites a Principal IO/Clocking Design Engineer to push the speed limits of high‑speed circuits used in DRAM products. You will design, optimize, verify, and fan out IO and clocking paths, develop modeling methods, and collaborate with Product Engineering and SI teams to align silicon performance with specs.

This senior role requires MSEE with 10+ years or BSEE with 12+ years, proficiency in Cadence, UNIX, and strong communication; mentoring and scripting

Qualifications

• Minimum MSEE with 10+ years in analog/mixed-signal design.
• Proficiency with UNIX and Cadence design tools.
• Strong layout and timing knowledge for high-speed circuits.
• Mentoring and excellent communication skills.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits for DRAM products.
• Model, simulate and analyze IO/data paths and clocking paths at circuit and system levels.
• Collaborate with Product Engineering, SI, and process teams to align silicon with specs.

Skills

High-speed IO design

Analog/mixed-signal design

UNIX

Cadence

Communication skills

Mentoring

Scripting (Python/Perl)

Education

MSEE

BSEE

Tools

Cadence Virtuoso

SPICE simulators

Job description

Micron Technology in Boise, Idaho, invites a Principal IO/Clocking Design Engineer to push the speed limits of high‑speed circuits used in DRAM products. You will design, optimize, verify, and fan out IO and clocking paths, develop modeling methods, and collaborate with Product Engineering and SI teams to align silicon performance with specs.

This senior role requires MSEE with 10+ years or BSEE with 12+ years, proficiency in Cadence, UNIX, and strong communication; mentoring and scripting