Senior IO Design Engineer – High-Speed Clocking for DRAM

Micron Technology, Inc.; Boise (ID); Híbrido; USD 150 000 - 210 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical/Dental/Vision plans

Paid time off

Paid holidays

Relocation assistance TBD

Resumo da oferta

Micron Technology, Inc. in Boise, Idaho, seeks a Principal IO/Clocking Design Engineer to lead development of high-speed IO and clocking circuits for DRAM products, performing modelling, verification and optimization across full-chip and system levels.

The role emphasizes strong fundamentals in analog/mixed-signal design, Cadence and UNIX, collaboration with product engineering, SI, and process teams, and mentoring junior engineers.

Qualificações

• Design, optimize and verify high-speed IO/clocking circuits for DRAM products.
• Deep understanding of device physics and CMOS processing techniques.
• Experience coordinating layout to minimize parasitics in high-speed paths.

Responsabilidades

• Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply proven high-speed circuit design techniques and evaluate IO/clocking performance at circuit and system levels.
• Develop modeling and simulation methods to capture key metrics and correlate with silicon.
• Collaborate with Product Engineering, SI and process teams on next-generation nodes.
• Mentor junior engineers and contribute to cross-team design reviews.

Conhecimentos

High-speed design

Analog/Mixed-signal

Cadence

Unix

Layout supervision

Technical communication

Formação académica

MSEE

BSEE

Ferramentas

Cadence

Descrição da oferta de emprego

Micron Technology, Inc. in Boise, Idaho, seeks a Principal IO/Clocking Design Engineer to lead development of high-speed IO and clocking circuits for DRAM products, performing modelling, verification and optimization across full-chip and system levels.

The role emphasizes strong fundamentals in analog/mixed-signal design, Cadence and UNIX, collaboration with product engineering, SI, and process teams, and mentoring junior engineers.