Senior IO & Clock Design Engineer – High-Speed DRAM IP

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off and holidays

Job summary

Micron Technology in Boise, Idaho, is seeking a Principal/MTs IO/Clock Design Engineer to lead the design, verification and optimization of high-speed IO and clocking circuits for DRAM IP. The role includes modeling, simulation, and cross-functional collaboration to ensure timing and performance goals are met.

You will mentor engineers, engage with process and transistor modeling teams, and contribute to AI-assisted design flows. Relocation to Micron's Boise headquarters is required.

Qualifications

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with strong background in designing high-speed IO interface, timing and clocking circuits.
• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts.
• Demonstrated ability to mentor and coach engineers.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply robust high-speed circuit design techniques and enhance timing/jitter sensitivity of the IO data path and clock path at circuit and full-chip level.
• Develop modeling, analysis and simulation methodologies to capture key circuit performance metrics and impact to product specs at full-chip level.
• Collaborate with product engineering and SI teams to compare silicon with simulation results and support correlation activities.
• Work with AI/ML tooling and scripting to improve design flows and circuit optimization.

Skills

High-speed IO design

Timing analysis

Clocking circuits

Mentoring

Education

MSEE

BSEE

Tools

PERL

Python

Job description

Micron Technology in Boise, Idaho, is seeking a Principal/MTs IO/Clock Design Engineer to lead the design, verification and optimization of high-speed IO and clocking circuits for DRAM IP. The role includes modeling, simulation, and cross-functional collaboration to ensure timing and performance goals are met.

You will mentor engineers, engage with process and transistor modeling teams, and contribute to AI-assisted design flows. Relocation to Micron's Boise headquarters is required.