Senior IO/Clock Design Engineer (SMTS) - High-Speed DRAM IP

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 150,000 - 200,000; Full time

Job summary

Micron Technology in Boise, Idaho seeks a Senior Principal/SMTS to lead IO and clock design for DRAM IP. You will define, design, optimize and verify high‑speed IO data paths and clock circuits, perform timing, jitter and budget analyses, and drive silicon validation with cross‑functional teams.

Relocation to Micron headquarters is required. You will mentor engineers, collaborate with Product Engineering, SI and process teams to advance next‑generation memory products and deliver robust,

Qualifications

• Minimum MSEE with 10+ years or BSEE with 12+ years of industry experience in high-speed IO/timing/clocking design.
• Ability to supervise layout and understand layout best practices for high-speed circuits.
• Strong communication skills for cross‑functional collaboration and mentoring.

Responsibilities

• Define, innovate, design, optimize and verify high‑speed IO and clocking circuits for DRAM products.
• Apply robust high‑speed circuit design techniques and enhance timing/jitter analysis for IO and clock paths.
• Develop modeling and simulation methodologies to capture key performance metrics and correlate with silicon results.

Skills

High-speed IO design

Timing/clock circuits

Mentoring engineers

Silicon validation

Education

MSEE

BSEE

Tools

PERL

Python

AI tools

Job description

Micron Technology in Boise, Idaho seeks a Senior Principal/SMTS to lead IO and clock design for DRAM IP. You will define, design, optimize and verify high‑speed IO data paths and clock circuits, perform timing, jitter and budget analyses, and drive silicon validation with cross‑functional teams.

Relocation to Micron headquarters is required. You will mentor engineers, collaborate with Product Engineering, SI and process teams to advance next‑generation memory products and deliver robust,