Senior IC Packaging Engineer - 2.5D/3D & TSV Expert

Avicena Tech; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Avicena is seeking a Senior IC Packaging Engineer in Sunnyvale, CA to lead architecture, design, and development of advanced semiconductor packaging solutions including 2.5D/3D IC, SiP, flip chip, and WLP. You will own TSV reveal processes, C4 bumping flows, and drive process control plans and yield improvements across optical engine packaging modules.

The role requires 5+ years in packaging or wafer fab engineering, strong cross-functional collaboration, and hands-on experience with metrology

Qualifications

• MS/PhD in materials or engineering related field.

Responsibilities

• Lead architecture, design, and development of advanced packaging solutions (2.5D/3D).
• Lead TSV reveal processes including back grind, CMP, dielectric reveal, and thickness control.
• Own C4 bumping flows for flip-chip and 3D-IC applications.
• Develop and maintain SPC, DOEs, and yield improvement roadmaps.
• Collaborate with design, reliability, and test teams to meet performance targets.
• Mentor junior engineers and contribute to documentation and best practices.

Skills

Cross-functional communication

Mentorship

Leadership

Education

MS/PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering or related field

Tools

CD-SEM

profilometer

XRF

AOI/SEM

Job description

Avicena is seeking a Senior IC Packaging Engineer in Sunnyvale, CA to lead architecture, design, and development of advanced semiconductor packaging solutions including 2.5D/3D IC, SiP, flip chip, and WLP. You will own TSV reveal processes, C4 bumping flows, and drive process control plans and yield improvements across optical engine packaging modules.

The role requires 5+ years in packaging or wafer fab engineering, strong cross-functional collaboration, and hands-on experience with metrology