Senior IC Layout Architect – RF/Analog Expert

Impinj; Seattle (WA); On-site; USD 159,000 - 238,000; Full time

Benefits offered by this job

Healthcare benefits

401(k) plan with company match

Stock options

Annual bonus

Remote work option

Job summary

Impinj is seeking a Senior Layout Design Engineer to join the Silicon Engineering team in Seattle. You will lead complex IC floorplanning and tapeout activities, coordinating with analog, digital, and process teams to deliver high-performance RFID silicon.

Ideal candidates have 12+ years of RF/mixed-signal layout experience, Cadence Virtuoso expertise, and a track record of successful tapeouts in advanced nodes.

Qualifications

• Bachelor’s or master’s degree in computer or electrical engineering or a related technical field.
• 12+ years of experience in custom analog, RF, and mixed-signal layout; lead complex ICs from conception to tapeout.
• Experience in tapeout flows with final database preparation and tapeout checklists.
• Ability to lead and mentor other layout engineers as the top-level floorplan/IC integration owner.
• Expert in full-chip/SOC-level floorplanning and integration — pin-ring generation, routing management, and full‑chip closure across intermediate hierarchies.
• Understanding of semiconductor manufacturing processes and foundry technologies down to 16nm for ultra-low-power/high-fidelity applications.
• Understanding of analog layout challenges and layout-dependent effects; proficiency with Cadence Virtuoso, Cadence/Siemens layout verification tools (PVS, Calibre DRC/LVS); interpreting ERC, DRC, LVS reports.
• Strong communication skills to collaborate with cross-functional teams.
• Demonstrated strong technical project management skills to prioritize tasks and deliver results.

Responsibilities

• Leverage Top-Down Bottom-Up floorplan methodology to create/refine the RFID/Reader IC floorplan, collaborating on sizing, pin rings, inter-block routing, and full-chip channels.
• Work with analog and digital design teams on floor planning, pin placement, power strategy and signal distribution between blocks.
• Coordinate with program managers and cross-functional teams to track layout activities to a predictable schedule and lead a successful tape-out.
• Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling; complete full‑chip closure, seal-ring, and DRC/LVS checks.
• Perform detailed transistor-level layout of RF, mixed-signal, and analog blocks for high-performance RF and ultra-low power RFID.
• Participate in the IC layout methodology roadmap with technology, CAD, and design teams to balance execution with long-term goals.

Skills

Custom analog layout

RF/mixed-signal layout

Tapeout flows

Floorplanning/IC integration

Full-chip/SOC floorplanning

Process nodes 16nm

Layout verification tools (DRC/LVS)

Cadence Virtuoso

ERC/DRC/LVS interpretation

Cross-functional communication

Technical project management

Education

Bachelor’s or Master’s in EE/CS

Tools

Cadence Virtuoso

Cadence/Siemens DRC/LVS

PVS

Siemens Calibre

Job description

Impinj is seeking a Senior Layout Design Engineer to join the Silicon Engineering team in Seattle. You will lead complex IC floorplanning and tapeout activities, coordinating with analog, digital, and process teams to deliver high-performance RFID silicon.

Ideal candidates have 12+ years of RF/mixed-signal layout experience, Cadence Virtuoso expertise, and a track record of successful tapeouts in advanced nodes.