RFIC Layout Designer – Analog & RF ICs (50GHz+)

InvestedintheMission; Redmond (WA); On-site; USD 105,000 - 175,000; Full time

Benefits offered by this job

Company shuttles

3 weeks paid vacation

10+ paid holidays

Medical, Vision, Dental

401(k) retirement plan

Stock options / long-term incentives

Job summary

SpaceX in Redmond is seeking an RFIC Layout Designer to lead the discipline of layout for RFIC and mixed-signal designs. You will collaborate with IC designers and chip leads on floor planning, power distribution, and pad locations for full-chip layouts.

The role emphasizes matching, minimizing parasitics, and hands-on layout verification across multiple silicon projects. Strong analog layout skills and experience with advanced nodes are required.

Qualifications

• Bachelor’s degree in electrical or computer engineering, or 3+ years in IC layout if no degree.
• Experience with layout of RF/analog blocks and attention to matching.

Responsibilities

• Determine chip floor plan including power/ground distribution and pad locations with packaging.
• Estimate schedule for layout work and identify complex areas early.
• Layout of custom RF and analog blocks with focus on matching and minimizing parasitics.
• Perform layout vs schematic, electrical rule checks, and fix errors.
• Complete top-level layout with ESD structures, pads, density fill, and tape-out readiness.
• Collaborate with EDA vendors to trial new tools and features.
• Create guides and demos to improve layout techniques.

Skills

Analog layout

RF/mixed signal

Floorplanning

Parasitic minimization

Independent problem solving

Education

Bachelors in electrical or computer engineering

Tools

Shell scripting

Python

Perl

Job description

SpaceX in Redmond is seeking an RFIC Layout Designer to lead the discipline of layout for RFIC and mixed-signal designs. You will collaborate with IC designers and chip leads on floor planning, power distribution, and pad locations for full-chip layouts.

The role emphasizes matching, minimizing parasitics, and hands-on layout verification across multiple silicon projects. Strong analog layout skills and experience with advanced nodes are required.