Senior RFIC Layout Architect

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

SpaceX is seeking a Sr. RFIC Layout Designer (RFIC Engineering) to lead the discipline of layout across multiple silicon projects.

You will collaborate with RFIC/mixed-signal designers on full-chip layouts of custom analog and RFIC designs for space and ground applications. You will work with cross-disciplinary teams to optimize floorplans, power distribution, and parasitic reduction, while driving design-rule checks and tape-out readiness.

Qualifications

• Bachelor’s degree in electrical or computer engineering with 5+ years IC layout design, or 8+ years experience in lieu of degree.
• Experience with advanced node IC layouts (22nm, 16nm, 7nm, 5nm or below).
• Experience with RF and analog circuit blocks layout and matching techniques.
• Strong communication and collaboration with cross-functional teams.

Responsibilities

• Determine chip floor plan including power and ground distribution and pad locations.
• Estimate layout schedule and identify areas of complexity early.
• Layout custom RF and analog blocks with attention to matching and parasitic minimization.
• Perform DRC/EIR LVS and layout vs schematic checks and resolve errors.
• Integrate top-level layout with ESD structures and pad assembly; support tape-out.

Skills

Analog layout

RFIC layout

Layout verification

Scripting (Python/Perl/Shell)

Education

Bachelor’s degree in electrical or computer engineering

Job description

SpaceX is seeking a Sr. RFIC Layout Designer (RFIC Engineering) to lead the discipline of layout across multiple silicon projects.

You will collaborate with RFIC/mixed-signal designers on full-chip layouts of custom analog and RFIC designs for space and ground applications. You will work with cross-disciplinary teams to optimize floorplans, power distribution, and parasitic reduction, while driving design-rule checks and tape-out readiness.