Senior IC Layout Architect - Remote

Impinj; United States; Hybrid; USD 158,700 - 238,100; Full time

Benefits offered by this job

Healthcare benefits

401(k) with company match

Remote-friendly policy

Job summary

Impinj is seeking a senior Layout Design Engineer to lead IC floorplanning for RFID and reader ICs. You will collaborate with analog and digital teams to optimize power, routing, and tape-out quality, while mentoring junior engineers.

The role emphasizes full-chip layout ownership, strategy development for AOT and DOT, and tight integration with manufacturing and foundry partners. This position offers hybrid work options and competitive benefits.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field with 12+ years of experience.
• Expert in custom analog, RF, and mixed-signal layout; able to lead complex ICs from conception to tapeout.
• Proficient in tapeout flows, final database prep, and tapeout checklists.
• Strong ability to mentor other layout engineers and coordinate with circuit designers.

Responsibilities

• Create/refine RFID/Reader IC floorplans using Top-Down Bottom-Up methodology.
• Collaborate with analog/digital design on floor planning, pin placement, power strategy, and signal distribution.
• Coordinate with program managers and cross-functional teams to track layout activities and meet tape-out schedules.
• Conduct layout reviews for power/ground routing, EMIR, matching, and signal integrity; manage DRC/LVS and density checks.
• Perform transistor-level layout of RF, mixed-signal, and analog blocks for high-performance RF and ultra-low power RFID.
• Contribute to layout methodology roadmap balancing short-term execution and long-term goals.

Skills

Floorplan leadership

Cadence Virtuoso

Tapeout management

RF/mixed-signal layout

DRC/LVS debugging

Mentoring

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence Virtuoso

Calibre DRC/LVS

PVS

Job description

Impinj is seeking a senior Layout Design Engineer to lead IC floorplanning for RFID and reader ICs. You will collaborate with analog and digital teams to optimize power, routing, and tape-out quality, while mentoring junior engineers.

The role emphasizes full-chip layout ownership, strategy development for AOT and DOT, and tight integration with manufacturing and foundry partners. This position offers hybrid work options and competitive benefits.