RFIC Layout Engineer for Space-Grade RF & Analog

United States Digital Space LLC; United States; On-site; USD 105,000 - 175,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical coverage

Job summary

United States Digital Space LLC is seeking an RFIC Layout Designer to join our IC design team. You will lead the discipline of layout for full-chip analog and RFIC blocks, coordinating with RFIC designers on floor planning, power distribution, and pad locations for space-grade silicon.

You will work with teams across architecture, verification, and manufacturing to ensure low parasitic layouts, tight matching, and successful tape-out.

Qualifications

• Bachelor’s degree in electrical or computer engineering and 1+ years of professional IC layout experience.
• Alternatively 3+ years of IC layout experience in lieu of a degree.
• Experience with advanced node IC layouts (22nm, 16nm, 7nm, 5nm or below).
• Experience with RF/mixed-signal layouts and high-frequency blocks up to 50GHz.

Responsibilities

• Define chip floor plan with power/ground distribution and pad locations with packaging input.
• Estimate layout schedule and flag areas needing early investigation.
• Layout of custom RF and analog blocks with emphasis on matching and parasitic control.
• Perform DRC, ERC, LVS checks and fix errors.
• Coordinate top-level layout with ESD structures and pad assembly; tape-out and density fill.
• Collaborate with EDA vendors to trial new tools and share layout improvements.

Skills

Strong analog layout skills

Excellent communication skills

Ability to work independently

Education

Bachelor’s degree in electrical or computer engineering

1+ years of professional IC layout experience

Tools

Linux

Shell scripting

Python

Perl

Git version control

Job description

United States Digital Space LLC is seeking an RFIC Layout Designer to join our IC design team. You will lead the discipline of layout for full-chip analog and RFIC blocks, coordinating with RFIC designers on floor planning, power distribution, and pad locations for space-grade silicon.

You will work with teams across architecture, verification, and manufacturing to ensure low parasitic layouts, tight matching, and successful tape-out.