Senior RFIC Layout Engineer — High-Freq Analog Design

InvestedintheMission; Redmond (WA); On-site; USD 140,000 - 235,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical coverage

Vision & dental

Parental leave

Paid vacation

Holidays

Shuttle service

Job summary

SpaceX is seeking a Sr. RFIC Layout Designer to join the RFIC engineering team in Redmond. You will lead the discipline of layout for mixed-signal ICs, collaborating with architecture, ASIC design, firmware, and pre/post-silicon teams on multiple silicon projects.

Responsibilities include defining floor plans, estimating schedules, layout of RF blocks, DRC/LVS checks, and final tape-out. Preferred candidates have 5+ years of IC layout, experience with 22nm+ nodes, and strong analog layout

Qualifications

• Bachelor’s degree in electrical or computer engineering with 5+ years of IC layout experience.
• Or 8+ years of professional IC layout experience in lieu of a degree.
• Experience with 22nm/16nm/7nm or smaller nodes.
• Experience with RF blocks like LNAs, VCOs and mixers.

Responsibilities

• Define floor plan with power and ground strategies.
• Estimate schedule and identify complex areas early.
• Layout of RF and analog blocks with emphasis on matching and parasitics.
• Perform DRC, ERC and LVS checks and resolve errors.
• Top-level layout integration with ESD structures and pad assembly; tape-out.
• Collaborate with EDA vendors to trial new tools.

Skills

Analog layout

Advanced nodes

RF block layout

RF frequencies up to 50GHz

LNA/VCO/Mixer layout

Skill programming

Scripting (Python/Perl)

Revision control

Circuit design

Linux

Communication

Independent work

Education

Bachelors in Electrical/Computer Engineering

Job description

SpaceX is seeking a Sr. RFIC Layout Designer to join the RFIC engineering team in Redmond. You will lead the discipline of layout for mixed-signal ICs, collaborating with architecture, ASIC design, firmware, and pre/post-silicon teams on multiple silicon projects.

Responsibilities include defining floor plans, estimating schedules, layout of RF blocks, DRC/LVS checks, and final tape-out. Preferred candidates have 5+ years of IC layout, experience with 22nm+ nodes, and strong analog layout