Senior IC Layout Architect - Lead Tapeout & Floorplanning

Impinj; Seattle (WA); On-site; USD 158,700 - 238,100; Full time

Benefits offered by this job

Healthcare benefits

401(k) plan with company match

Job summary

Impinj, a leading RFID and IoT company, seeks a senior Layout Design Engineer to own floorplanning and integration for RFID/Reader ICs. You will collaborate with analog and digital teams, shaping layout strategies and guiding tapeouts to high yields and reliable silicon.

The role demands 12+ years in analog/RF/mixed‑signal layout, Cadence Virtuoso proficiency, and strong mentorship skills. Expect global teamwork, fast pacing, and impactful silicon development.

Qualifications

• Bachelors or Masters in computer or electrical engineering or related field.
• 12+ years of experience in custom analog, RF, and mixed‑signal layout.
• Lead complex ICs from conception to tapeout.
• Mentor other layout engineers and coordinate with circuit designers.
• Proficient in full‑chip/SOC‑level floorplanning and integration, routing, and block integration.

Responsibilities

• Leverage TDBU floorplan to create/refine RFID/Reader IC floorplan with layout designers.
• Collaborate with analog/digital teams on floor planning, pin placement, and power distribution.
• Coordinate with program managers and cross‑functional teams to track layout activities and tape‑out schedule.
• Conduct layout reviews for power/ground routing, electromigration, and signal integrity; perform full‑chip closure, DRC/LVS checks.
• Perform transistor‑level layout for RF, mixed‑signal, and analog blocks for high‑performance RF and ultra‑low power RFID.
• Participate in layout methodology roadmap with tech, CAD, and design teams.

Skills

Floorplanning leadership

RF/mixed-signal layout

Tapeout coordination

Cross‑functional collaboration

Mentoring peers

Education

Bachelor’s or Master’s in EE or related

Tools

Cadence Virtuoso

Calibre (DRC/LVS)

Siemens Calibre

Job description

Impinj, a leading RFID and IoT company, seeks a senior Layout Design Engineer to own floorplanning and integration for RFID/Reader ICs. You will collaborate with analog and digital teams, shaping layout strategies and guiding tapeouts to high yields and reliable silicon.

The role demands 12+ years in analog/RF/mixed‑signal layout, Cadence Virtuoso proficiency, and strong mentorship skills. Expect global teamwork, fast pacing, and impactful silicon development.