Senior HLS Verification Engineer for Video Codec ASICs

Socket.dev; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is seeking a Design Verification engineer to verify custom video codec ASICs for YouTube, bridging algorithmic intent and hardware. You will manage a High-Level Synthesis workflow, using C/C++ tests, co-simulation, and UVM testbenches to guarantee equivalence and compliance.

You will own the verification lifecycle from architectural planning to coverage closure. Role lies within the Argos IP team, contributing to high-performance silicon with rapid iteration, while collaborating across

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 8 years of experience with Design Verification.
• Experience with SystemVerilog and UVM.

Responsibilities

• Lead comprehensive verification strategies and signoff for complex blocks from C/C++ to RTL.
• Design and maintain environments using GoogleTest and SystemVerilog/UVM for RTL timing.
• Apply HLS methods such as C/RTL co-simulation and formal equivalence verification.
• Drive debugging and coverage analysis across C++ and RTL domains to verify design transformations.
• Collaborate with design teams to optimize C++ for verifiability and mentor junior engineers on HLS verification.

Skills

Design Verification

SystemVerilog

UVM

C/C++

HLS verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Equivalent practical experience

Master's degree or PhD with computer architecture emphasis

Tools

Catapult

Vivado

XLS

VCS

Xcelium

Verdi

Job description

Google is seeking a Design Verification engineer to verify custom video codec ASICs for YouTube, bridging algorithmic intent and hardware. You will manage a High-Level Synthesis workflow, using C/C++ tests, co-simulation, and UVM testbenches to guarantee equivalence and compliance.

You will own the verification lifecycle from architectural planning to coverage closure. Role lies within the Argos IP team, contributing to high-performance silicon with rapid iteration, while collaborating across