Senior Silicon Design Verification Engineer, YouTube Video Accelerators

Google; Mountain View (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Google in Mountain View, CA is seeking a Senior Silicon Design Verification Engineer for YouTube Video Accelerators. The role focuses on verification strategies spanning HLS to RTL with c/c++ environments and UVM methodologies.

Candidates should bring deep expertise in C/C++ and RTL verification to drive high-quality silicon for consumer products. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits.

Qualifications

• Bachelor's degree or equivalent practical experience in Electrical/Computer Engineering, Computer Science, or related field.
• 8 years of experience in verification methodologies and languages such as UVM and SystemVerilog.

Responsibilities

• Lead verification strategies and signoff for complex blocks from HLS to RTL.
• Design and maintain environments using C/C++ GoogleTest and SystemVerilog/UVM for RTL timing and system interactions.
• Use HLS methods like C/RTL co-simulation and formal equivalence verification to ensure hardware fidelity.
• Perform bug hunting and coverage analysis across C++ and RTL domains to verify design transformations.
• Mentor engineers on HLS verification and optimize C++ code for verification.

Skills

UVM

SystemVerilog

C/C++

RTL verification

Education

Bachelor's degree in Electrical/Computer Engineering/Computer Science

Tools

VCS

Xcelium

Verdi

Job description

Senior Silicon Design Verification Engineer, YouTube Video Accelerators

Corporate fare: YouTube

Place: Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in test planning and testbench architecture using SystemVerilog and UVM, including coverage-driven and constrained random testing.
• Experience with High-Level Synthesis tools (e.g., Catapult, Vivado, XLS).
• Experience in video processing, image pipelines, or video compression standards such as AV1, AV2, or H.264.
• Ability to debug complex issues across C/C++ and RTL levels using industry-standard EDA tools like VCS, Xcelium, or Verdi.
• Excellent C/C++ skills for developing HLS testbenches and models.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. At YouTube, we believe that everyone deserves to have a voice, and that the world is a better place when we listen, share, and build community through our stories. We work together to give everyone the power to share their story, explore what they love, and connect with one another in the process. Working at the intersection of cutting-edge technology and boundless creativity, we move at the speed of culture with a shared goal to show people the world. We explore new ideas, solve real problems, and have fun – and we do it all together.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead comprehensive verification strategies and signoff for complex blocks where the source is C/C++, taking full ownership of quality from High-Level Synthesis (HLS) code to generated Register-Transfer Level (RTL).
• Design and maintain advanced environments, including C/C++ GoogleTest for functional validation and SystemVerilog/Universal Verification Methodology (UVM) for RTL timing and system interactions.
• Employ HLS-specific methods such as C/RTL co-simulation, formal equivalence verification, and transaction-level modeling to ensure hardware fidelity.
• Drive complex bug hunting and coverage analysis across both C++ and RTL domains to ensure complete verification of the design transformation.
• Partner with design teams to optimize C++ code for verification and mentor engineers on the nuances of HLS verification.

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