Senior Silicon Verification Architect (HLS/RTL)

Google; Mountain View (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Google in Mountain View, CA is seeking a Senior Silicon Design Verification Engineer for YouTube Video Accelerators. The role focuses on verification strategies spanning HLS to RTL with c/c++ environments and UVM methodologies.

Candidates should bring deep expertise in C/C++ and RTL verification to drive high-quality silicon for consumer products. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits.

Qualifications

• Bachelor's degree or equivalent practical experience in Electrical/Computer Engineering, Computer Science, or related field.
• 8 years of experience in verification methodologies and languages such as UVM and SystemVerilog.

Responsibilities

• Lead verification strategies and signoff for complex blocks from HLS to RTL.
• Design and maintain environments using C/C++ GoogleTest and SystemVerilog/UVM for RTL timing and system interactions.
• Use HLS methods like C/RTL co-simulation and formal equivalence verification to ensure hardware fidelity.
• Perform bug hunting and coverage analysis across C++ and RTL domains to verify design transformations.
• Mentor engineers on HLS verification and optimize C++ code for verification.

Skills

UVM

SystemVerilog

C/C++

RTL verification

Education

Bachelor's degree in Electrical/Computer Engineering/Computer Science

Tools

VCS

Xcelium

Verdi

Job description

Google in Mountain View, CA is seeking a Senior Silicon Design Verification Engineer for YouTube Video Accelerators. The role focuses on verification strategies spanning HLS to RTL with c/c++ environments and UVM methodologies.

Candidates should bring deep expertise in C/C++ and RTL verification to drive high-quality silicon for consumer products. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits.