Senior Silicon Design Verification Engineer, YouTube Video Accelerators

Google Inc.

Mountain View (CA)

On-site

USD 142,000 - 236,000

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Job summary

Google Mountain View seeks a Senior Silicon Design Verification Engineer for YouTube Video Accelerators to own verification across C/C++ and RTL, bridging algorithmic intent with hardware implementation. You will lead HLS verification workflows, develop advanced testbenches, and collaborate with design teams to ensure high-quality silicon for video workflows.

The role emphasizes ownership of verification life-cycle, from planning to coverage closure, with expertise in SystemVerilog/UVM, C/C++,

Qualifications

  • Bachelor's degree or equivalent practical experience.
  • 8 years of design verification experience.
  • Experience with SystemVerilog and UVM.

Responsibilities

  • Lead comprehensive verification strategies and signoff for complex blocks from C/C++ to RTL.
  • Develop and maintain environments using C/C++ GoogleTest for functional validation and SystemVerilog/UVM for RTL timing and interactions.
  • Use HLS methods such as C/RTL co-simulation and formal equivalence verification to ensure hardware fidelity.
  • Drive bug hunting and coverage analysis across C++ and RTL domains to ensure complete verification.
  • Mentor junior engineers on HLS verification and optimize C++ code for verifiability.

Skills

SystemVerilog
UVM
Design verification
C/C++

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's degree or PhD in Electrical/Computer Engineering or Computer Science (preferred)

Tools

VCS
Xcelium
Verdi

Job description

Senior Silicon Design Verification Engineer, YouTube Video Accelerators
  • Copy link

YouTube Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

  • Copy link
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with Design Verification.
  • Experience with SystemVerilog and Universal Verification Methodology (UVM).
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Practical experience with High-Level Synthesis tools (e.g., Catapult, Vivado, XLS) and strong C/C++ skills for developing HLS testbenches and models.
  • Expertise in video processing, image pipelines, or video compression standards such as AV1, AV2, or H.264.
  • Demonstrated ability to debug complex issues across C/C++ and RTL levels using industry-standard EDA tools like VCS, Xcelium, or Verdi.
About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a part of the Design Verification (DV) role in the Argos IP team, you will ensure the functional correctness of custom video codec ASICs for YouTube by managing a specialized High-Level Synthesis (HLS) workflow that requires verification at both the C/C++ and RTL levels. You will be responsible for bridging the gap between algorithmic intent and hardware implementation, employing a hybrid strategy that includes C++ software testing, C/RTL co-simulation, and traditional SystemVerilog/ Universal Verification Methodology (UVM) testbenches to guarantee equivalence and compliance. Your role demands comprehensive ownership of the verification life-cycle, from architectural planning and mixed-abstraction debugging to final coverage closure, while continuously refining methodologies to handle the specific complexities of HLS-based silicon design. At YouTube, we believe that everyone deserves to have a voice, and that the world is a better place when we share, and build community through our stories. We work together to give everyone the power to share their story, explore what they love, and connect with one another in the process. Working at the intersection of cutting-edge technology and boundless creativity, we move at the speed of culture with a shared goal to show people the world. We explore new ideas, solve real problems, and have fun — and we do it all together.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

  • Lead comprehensive verification strategies and signoff for complex blocks where the source is C/C++, taking full ownership of quality from HLS code to generated RTL.
  • Design and maintain advanced environments, including C/C++ GoogleTest for functional validation and SystemVerilog/UVM for RTL timing and system interactions.
  • Employ HLS-specific methods such as C/RTL co-simulation, formal equivalence verification, and transaction-level modeling to ensure hardware fidelity.
  • Drive complex bug hunting and coverage analysis across both C++ and RTL domains to ensure complete verification of the design transformation.
  • Partner with design teams to optimize C++ code for verifiability and mentor junior engineers on the nuances of HLS verification.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Senior Silicon Design Verification Engineer, YouTube Video Accelerators
Senior Silicon Design Verification Engineer, YouTube Video Accelerators

Google • Mountain View (CA)

On-site
USD 156,000 - 229,000
Senior Design Verification Engineer, Silicon
Senior Design Verification Engineer, Silicon

Google • Mountain View (CA)

On-site
USD 150,000 - 223,000
Senior Silicon DV Engineer — Video Codec & HLS
Senior Silicon DV Engineer — Video Codec & HLS

Google Inc. • Mountain View (CA)

On-site
USD 142,000 - 236,000
Silicon Design Verification Manager
Silicon Design Verification Manager

Google • Austin (TX)

Hybrid
USD 192,000 - 278,000
Bonus target
Equity
Benefits
Senior Silicon Verification Architect (HLS/RTL)
Senior Silicon Verification Architect (HLS/RTL)

Google • Mountain View (CA)

On-site
USD 156,000 - 229,000
Senior Design Engineer, RTL
Senior Design Engineer, RTL

Google • Mountain View (CA)

On-site
USD 163,000 - 236,000
Senior ASIC Design Verification Engineer, Cloud
Senior ASIC Design Verification Engineer, Cloud

Google Inc. • Sunnyvale (CA)

On-site
USD 163,000 - 236,000
Senior Design Verification CAD Engineer, Silicon, Google Cloud
Senior Design Verification CAD Engineer, Silicon, Google Cloud

Google Inc. • Sunnyvale (CA)

On-site
USD 163,000 - 237,000
15% bonus target
equity
benefits
ASIC Design Verification Technical Lead, High-Speed DSP
ASIC Design Verification Technical Lead, High-Speed DSP

Google • Sunnyvale (CA)

Hybrid
USD 240,000 - 333,000
Senior ASIC Design Verification Engineer, Google Cloud
Senior ASIC Design Verification Engineer, Google Cloud

Google Inc. • Sunnyvale (CA)

On-site
USD 156,000 - 229,000