Senior High-Speed Memory & Cache Controller Engineer

Anysilicon; San Diego (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Senior ASIC Design Engineer to join its ASICS Engineering team. This role focuses on designing high‑speed memory controllers for next‑generation products and advancing Qualcomm’s data processing capabilities.

You will define, model, design, verify, and document IP, implement RTL for high‑speed memory systems, drive micro‑architecture, and collaborate with verification and physical design during integration.

Qualifications

• Bachelor’s or Master’s degree in Science, Engineering, or related field.
• 3+ years of ASIC design experience or recent graduates encouraged to apply.

Responsibilities

• Define, model, design, verify, validate, implement, and document IP development for high‑performance products.
• Work on architecture, RTL coding, and deployment of high‑speed memory systems into QCT products.
• Develop architecture and design specifications and drive micro-architecture of logic design.
• Implement and deliver RTL, collaborating with verification engineers to ensure high-quality designs.
• Debug designs and provide support during integration into the chip.
• Conduct synthesis, timing closure, physical design support, and power analysis.
• Contribute to improvements in design methodology to enhance productivity and quality.

Skills

LPDDR memory

Cache controller design

NoC architectures

Front-end interfacing

HBM memory

SRAM & L3 cache

x86/ARM architectures

Memory ordering

Education

Bachelor's or Master's degree in Science/Engineering

Job description

Qualcomm Technologies, Inc. is seeking a Senior ASIC Design Engineer to join its ASICS Engineering team. This role focuses on designing high‑speed memory controllers for next‑generation products and advancing Qualcomm’s data processing capabilities.

You will define, model, design, verify, and document IP, implement RTL for high‑speed memory systems, drive micro‑architecture, and collaborate with verification and physical design during integration.