Senior ASIC Designer, High-Speed Memory Subsystems (HBM/LPDDR)

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Annual discretionary bonus

Annual RSU grants

Extensive benefits package

Job summary

Qualcomm is seeking a Senior ASIC Design Engineer to develop high-speed memory and cache controller designs. The role involves architecture, RTL coding, and collaboration with verification teams to ensure high-quality outputs.

The ideal candidate will have a Bachelor's or Master's in Engineering with at least 5 years of ASIC design experience. The position offers a competitive salary range of $140,000 to $210,000 along with additional bonuses and extensive benefits.

Qualifications

• 5+ years ASIC design, RTL coding, and front-end digital design experience.
• 3+ years Hardware Architecture experience.
• Exposure to RTL Design Verification flows.

Responsibilities

• Debugging designs and providing integration support.
• Implementing and delivering RTL for high-speed memory subsystems.
• Driving micro-architecture of logic designs.

Skills

ASIC design

RTL coding

Front-end digital design

Hardware Architecture

High-speed digital design

LPDDR memory design

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Computer Engineering or Electrical Engineering

Job description

Qualcomm is seeking a Senior ASIC Design Engineer to develop high-speed memory and cache controller designs. The role involves architecture, RTL coding, and collaboration with verification teams to ensure high-quality outputs.

The ideal candidate will have a Bachelor's or Master's in Engineering with at least 5 years of ASIC design experience. The position offers a competitive salary range of $140,000 to $210,000 along with additional bonuses and extensive benefits.