Senior Memory & Cache Controller ASIC Designer

QUALCOMM, Inc.; San Diego (CA); On-site; USD 101,000 - 152,000; Full time

Benefits offered by this job

Annual discretionary bonus

RSU grants

Benefits package

Job summary

Qualcomm Technologies, Inc. is seeking a Senior ASIC Design Engineer for next-generation high-speed memory controllers, interfacing with CPUs, GPUs, DSPs, and multimedia processors.

The role focuses on architecture, RTL coding, and deployment of high-speed memory systems in Qualcomm products. The candidate will work on memory controllers (LPDDR, HBM/DDR), NoC-based architectures, and cross-functional collaboration to deliver high-quality designs, with emphasis on timing, synthesis, and debug

Qualifications

• Bachelor's or Master's degree in Science, Engineering, or related field.
• Team welcomes recent graduates and 3+ years of experience.

Responsibilities

• Define, model, design (digital and/or analog), verify, validate, implement and document IP (block/SoC).
• Synthesize timing, perform physical design support, and debug designs.
• Collaborate with cross-functional teams to determine product execution path.

Skills

LPDDR memory

HBM memory

NoC architectures

x86/ARM CPU

RTL design

Education

Master's in Computer Engineering or Electrical Engineering

Bachelor's degree in Science, Engineering, or related field

Tools

Verilog/VHDL

Job description

Qualcomm Technologies, Inc. is seeking a Senior ASIC Design Engineer for next-generation high-speed memory controllers, interfacing with CPUs, GPUs, DSPs, and multimedia processors.

The role focuses on architecture, RTL coding, and deployment of high-speed memory systems in Qualcomm products. The candidate will work on memory controllers (LPDDR, HBM/DDR), NoC-based architectures, and cross-functional collaboration to deliver high-quality designs, with emphasis on timing, synthesis, and debug