Senior High-Speed Memory Controller ASIC Engineer

Qualcomm; San Diego (CA); On-site; USD 140,000 - 230,000; Full time

Benefits offered by this job

Annual bonus program

RSU grants

Benefits package

Job summary

Qualcomm Technologies, Inc. in San Diego is seeking a Senior ASIC Design Engineer to contribute to next generation memory controller designs (HBM/LPDDR/DDR) at frequencies above 1 GHz.

You will work on RTL coding, architecture, and verification, collaborating with CPU, GPU, DSP teams, and drive synthesis, timing, and power analysis while delivering high quality ASICs. Requirements include 4+ years (Bachelor) or more with MS/PhD options; strong background in ASIC design and front-end digital

Qualifications

• Bachelor's or Masters degree in Science, Engineering, or related field.
• 5+ years ASIC design, RTL coding, front-end digital design experience
• 3+ years Hardware Architecture experience
• PhD in Science, Engineering, or related field and 2+ years experience (if applicable)

Responsibilities

• Architect, design (RTL coding), and deploy next-gen high-speed memory systems in Qualcomm products.
• Develop or contribute to architecture and design specifications and drive micro-architecture of design portions.
• Implement and deliver RTL and collaborate with verification engineers to deliver high-quality designs.
• Debug designs and provide debug support during integration.
• Perform Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis; drive design methodology improvements.

Skills

ASIC design

RTL coding

front-end digital design

Power analysis

Synthesis and timing closure

Education

Master's degree in Computer/Electrical Engineering

Bachelor's degree in Science/Engineering

PhD in Science/Engineering

Tools

RTL Design Verification flows

x86/ARM CPU architectures

Job description

Qualcomm Technologies, Inc. in San Diego is seeking a Senior ASIC Design Engineer to contribute to next generation memory controller designs (HBM/LPDDR/DDR) at frequencies above 1 GHz.

You will work on RTL coding, architecture, and verification, collaborating with CPU, GPU, DSP teams, and drive synthesis, timing, and power analysis while delivering high quality ASICs. Requirements include 4+ years (Bachelor) or more with MS/PhD options; strong background in ASIC design and front-end digital